The present invention relates in general to semiconductor fabrication methods and resulting structures. More specifically, the present invention relates to complementary metal oxide semiconductor (CMOS) boundary protection for vertical tunneling field effect transistors.
In an integrated circuit, transistors such as metal oxide semiconductor field effect transistors (MOSFETs) have a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. Complementary metal oxide semiconductor (CMOS) is a technology that uses complementary and symmetrical pairs of p-type and n-type MOSFETs to implement logic functions. The channel region connects the source and the drain, and electrical current flows through the channel region from the source to the drain. The electrical current flow is induced in the channel region by a voltage applied at the gate electrode. Multi-threshold CMOS (MTCMOS) is a variation of CMOS chip technology that has transistors with multiple threshold voltages (Vth) in order to optimize delay or power.